1. Technical Field
The embodiment described herein relates to a semiconductor integrated circuit, particularly a semiconductor memory apparatus.
2. Related Art
A conventional semiconductor memory apparatus, as shown in FIG. 1, is configured to include an address buffer 10, a command buffer 20, and a data buffer 30.
The address buffer 10 generates an internal address ‘add_int’ by buffering an external address ‘add_ext’ in accordance with a first external reference voltage ‘Vref_ext1’.
The command buffer 20 generates an internal command ‘com_int’ by buffering an external command ‘com_ext’ in accordance with the first external reference voltage ‘Vref_ext1’.
The data buffer 30 generates an internal data ‘data_int’ by buffering an external data ‘data_ext’ in accordance with a second external reference voltage ‘Vref_ext2’.
The external address ‘add_ext’, the external command ‘com_ext’, the external data ‘data_ext’, the first external reference voltage ‘Vref_ext1’, and the second external reference voltage ‘Vref_ext2’ are inputted from the outside of the semiconductor memory apparatus through corresponding pads, in which the first external reference voltage ‘Vref_ext1’ and the second external reference voltage ‘Vref_ext2’ may be at the same voltage level.
Due to the operational speed of semiconductor memory apparatuses rapidly increasing, in order to provide a stable operation of the semiconductor memory apparatuses, the semiconductor memory apparatuses are designed such that voltages are applied to a circuit that consumes large current and a circuit that consumes small current through different power sources.
The data buffer 30 consumes larger current than the address buffer 10 and the command buffer 20. Therefore, the first external reference voltage ‘Vref_ext1’ is applied to the address buffer 10 and the command buffer 20 and the second external reference voltage ‘Vref_ext2’ is applied to the data buffer 30.
Performing a test before the package state of semiconductor memory apparatuses, i.e. in the wafer state, is called a wafer test.
The semiconductor memory apparatuses are operated at a low speed because the test is performed by connecting a test device to the semiconductor memory apparatuses in the wafer test.
Semiconductor memory apparatuses designed to be supplied with the first external reference voltage ‘Vref_ext1’ and the second external reference voltage ‘Vref_ext2’ through different pads to perform a high-speed operation are supplied with the first and second external reference voltages ‘Vref_ext1’, ‘Vref_ext2’ from different pads in the wafer test performing a low-speed operation.
Conventional semiconductor memory apparatuses use the pad, which is needed for a high-speed operation, for a low-speed operation in the same way, such that the number of pads unnecessarily increases. Further, the number of lines connecting a test device with the semiconductor memory apparatus increases in the wafer test.